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- W1797086466 abstract "By reducing the parasitic node capacitances, the Branch-Based Logic design style can increase the performances of digital circuits. In order to benefit from the full potential of the design style and to be able to port it to different technologies, it is important to take into account the specific features of each technology. We investigate the case of three advanced 0.25 µm CMOS technologies: bulk, Partially-Depleted SOI and Fully-Depleted SOI. The design of a 16-bit carry-select Branch-Based adder IP is discussed. The Branch-Based adder shows lower power consumption compared to an implementation with conventional CMOS logic gates." @default.
- W1797086466 created "2016-06-24" @default.
- W1797086466 creator A5042791284 @default.
- W1797086466 creator A5064026729 @default.
- W1797086466 date "2002-01-01" @default.
- W1797086466 modified "2023-09-26" @default.
- W1797086466 title "Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies" @default.
- W1797086466 cites W1993623123 @default.
- W1797086466 doi "https://doi.org/10.1007/978-0-387-35597-9_15" @default.
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