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- W18001063 abstract "For the implementation of high-complexity circuits operating at high speed, low-power circuits are essential in order to meet chip level and systems level power dissipation requirements. This paper presents the designs of a multiplexer and a demultiplexer. The circuits are implemented by using two-phase dynamic FET logic (TDFL). Two chips were designed. Each chip comprises a small system integrating normal TDFL logic, pass gates and domino logic as well as clock drivers. Measurements show that the multiplexer operates at 300MHz and the demultiplexer operates at 550MHz" @default.
- W18001063 created "2016-06-24" @default.
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- W18001063 date "1994-04-01" @default.
- W18001063 modified "2023-09-26" @default.
- W18001063 title "Low-power GaAs multiplexer and demultiplexer" @default.
- W18001063 hasPublicationYear "1994" @default.
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