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• W1801353591 abstract "The hardening of a standard 1-/spl mu/m double layer metal CMOS SOI technology to a space environment is discussed. It is shown that a 50 krad(Si) hardened technology with VLSI performance can be obtained by changing a few steps in the basic process flow. Optimal results are obtained for a 850/spl deg/C gate oxidation, combined with MESA-LOCOS isolation. Results of the radiation tests, using a /sup 60/Co source, indicate changes in the threshold voltage of about 100 mV for a total dose of 100 krad(Si) and hole trapping factors in the range of 0.10-0.15. The increase in the low-frequency noise observed after irradiation is mainly related to the edge region of the MOS transistors. >" @default.
• W1801353591 created "2016-06-24" @default.
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• W1801353591 date "2002-12-30" @default.
• W1801353591 modified "2023-09-30" @default.
• W1801353591 title "Low-frequency noise and DC characterization of ionization damage in a 1-μm SOI CMOS technology adapted for space applications" @default.
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• W1801353591 doi "https://doi.org/10.1109/radecs.1993.316574" @default.
• W1801353591 hasPublicationYear "2002" @default.
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