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- W180262721 abstract "Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serious challenges. Multiprocessors-on-a-ProgrammableChip (MPoPCs), which integrate both softwareprogrammability and hardware-reconfigurability, provide substantial flexibility that can result in programming ease and high performance. This paper presents an application-oriented system design methodology for HERA (HEterogeneous Reconfigurable Architecture), an in-house developed MPoPC that targets applications involving large matrices. HERA is a mixed computing-mode multiprocessor supporting simultaneous execution in SIMD (Single-Instruction, MultipleData), MIMD (Multiple-Instruction, Multiple-Data), and multiple-SIMD for chosen groups of processors. Given an application with specific energy-performance objectives, our design methodology aims to customize HERA to match the diverse computation and communication characteristics of tasks in the application. Appropriate analysis of the application guides system synthesis that employs a parameterized hardware component library (PHCL) of function units with predictable performance and power dissipation. Extensive experimental results for parallel power-flow analysis are presented to demonstrate the effectiveness of our design methodology." @default.
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- W180262721 date "2007-01-01" @default.
- W180262721 modified "2023-09-24" @default.
- W180262721 title "Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors." @default.
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