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- W1808687495 abstract "We describe an extension of modulo scheduling, called “memory reference merging”, which improves the management of cache bandwidth on microprocessors such as the DEC Alpha 21164. The principle is to schedule together memory references that are likely to be merged in a read buffer (LOADs), or a write buffer (STOREs). This technique has been used over several years on the Cray T3E block scheduler, and was later generalized to the Cray T3E software pipeliner. Experiments on the Cray T3E demonstrate the benefits of memory reference merging." @default.
- W1808687495 created "2016-06-24" @default.
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- W1808687495 date "1999-01-01" @default.
- W1808687495 modified "2023-09-24" @default.
- W1808687495 title "Extending Modulo Scheduling with Memory Reference Merging" @default.
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- W1808687495 doi "https://doi.org/10.1007/978-3-540-49051-7_19" @default.
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