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- W1809255003 abstract "This paper presents a novel digit-serial-in-serial-out systolic array for performing the power-sum operation C+AB/sup 2/ in finite fields GF(2/sup m/) with the standard basis representation. If the appropriate digit-size is selected, the proposed method can meet the throughput requirement of a specific application with minimum hardware. With the digit size of the regular square form, the latency of the array can be reduced by 20% as before in GF(2/sup 160/). The new digit-serial systolic array with unidirectional data flow is highly regular, nearest-neighbor connected, and thus is well suited for VLSI implementation." @default.
- W1809255003 created "2016-06-24" @default.
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- W1809255003 date "2002-11-13" @default.
- W1809255003 modified "2023-09-26" @default.
- W1809255003 title "Digit-serial systolic power-sum array in GF(2/sup m/)" @default.
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- W1809255003 doi "https://doi.org/10.1109/icii.2001.983507" @default.
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