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- W1818923247 abstract "The paper reviews working principles of phase-locked loop and drawbacks of classical PLL structure in nanometric technologies. It is proposed to replace the classical structure by all-digital phase-locked loop structure. Authors described the main blocks of all-digital phase-locked loop (time to digital converter and digitally controlled oscillator) and overviewed the quantization noise arising in these blocks as well as its minimization strategies. The calculated inverter delay in 65 nm CMOS technology was from 8.64 to 27.71 ps and time to digital converter quantization noise was from −104.33 to −82.17 dBc/Hz, with tres = 8.64–27.71 ps, TSVG = 143–333 ps, FREF = 20–60 MHz. Article in Lithuanian. Santrauka Nagrinėjama fazės derinimo kilpa (FDK), jos veikimas, klasikinės struktūros FDK trūkumai nanometrinėse technologijose, galimi jų sprendimo būdai. Siūlomas perėjimas prie visiškai skaitmeninės fazės derinimo kilpos. Aprašomi pagrindiniai visiškai skaitmeninės FDK blokai – laikinis skaitmeninis keitiklis (LSK) ir skaitmeniniu būdu valdomas generatorius (SVG). Aptariamas LSK ir SVG atsirandantis kvantavimo triukšmas ir jo mažinimo priemonės. Apskaičiuota 65 nm KMOP technologijoje pasiekiama inverterio vėlinimo trukmė, lygi nuo 8,64 iki 27,71 ps, ir LSK triukšmo lygis, lygus nuo −104,33 iki −82,17 dBc/Hz, kai inverterio vėlinimo trukmė t res = 8,64–27,71 ps, SVG generuojamo signalo periodas TSVG = 143–333 ps, o atraminio signalo dažnis FREF = 20–60 MHz." @default.
- W1818923247 created "2016-06-24" @default.
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- W1818923247 date "2013-05-24" @default.
- W1818923247 modified "2023-10-18" @default.
- W1818923247 title "ALL DIGITAL PHASE-LOCKED LOOP / VISIŠKAI SKAITMENINĖ FAZĖS DERINIMO KILPA" @default.
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- W1818923247 doi "https://doi.org/10.3846/mla.2013.24" @default.
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