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- W1820430086 abstract "A 32-kb macro containing an eight-transistor soft error robust SRAM cell with differential read and write capabilities is presented. The 8T cell does not have dedicated access transistors, and its quad-latch configuration stores data on four interlocked storage nodes. The macro was designed in a 65-nm CMOS process. The cell demonstrates excellent read data stability down to 0.55 V and is well suited for low-voltage, low-power applications. Neutron radiation testing on the macro exhibits at least 15× improvement in Failure in Time (FIT) rate compared with the conventional 6T SRAM cell in 65-nm CMOS technology." @default.
- W1820430086 created "2016-06-24" @default.
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- W1820430086 date "2015-06-01" @default.
- W1820430086 modified "2023-10-05" @default.
- W1820430086 title "A 32 kb Macro with 8T Soft Error Robust, SRAM Cell in 65-nm CMOS" @default.
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- W1820430086 doi "https://doi.org/10.1109/tns.2015.2429589" @default.
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