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• W1822055675 abstract "Abstract We propose a method for in situ characterization of the photovoltaic module power at standard test conditions, using superposition of the dark current–voltage ( I–V ) curve measured at the elevated stress temperature, during potential‐induced degradation (PID) testing. PID chamber studies were performed on several crystalline silicon module designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the modules. The results using the superposition principle show a mismatch between the power degradation measured at stress temperature and the degradation measured at 25 °C, dependent on module design, stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum‐power temperature translation methods found in the literature. For the first method, which is based on the maximum‐power temperature coefficient, we find that the temperature coefficient changes as the module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two‐diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large‐scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum‐power temperature translation method, by taking advantage of the near‐linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids stress transients while ramping to and from the stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Copyright © 2015 John Wiley & Sons, Ltd." @default.
• W1822055675 created "2016-06-24" @default.
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• W1822055675 date "2015-01-21" @default.
• W1822055675 modified "2023-09-24" @default.
• W1822055675 title "Temperature‐dependency analysis and correction methods of <i>in situ</i> power‐loss estimation for crystalline silicon modules undergoing potential‐induced degradation stress testing" @default.
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• W1822055675 doi "https://doi.org/10.1002/pip.2587" @default.
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