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- W182448324 abstract "In order to exploit the fine-grain parallelism in pipelined, superscalar, superpipelined and VLIW machines, various strategies for scheduling instructions at compile time have been developed. Unfortunately, these strategies can have a negative effect on register allocation which is one of the most important optimizations performed in optimizing compilers. Until recently instruction scheduling and register allocation were treated separately, one occurring before the other in isolation. Due to the conflicts in ordering these two phases, several efforts have been made to provide communication between instruction scheduling and register allocation. However, the current schemes suffer a number of drawbacks.This dissertation investigates these issues through several strategies to provide cooperation between register allocation and instruction scheduling. One strategy, a Scheduler Sensitive Global register allocator (SSG), provides cooperation between global register allocation and per basic block instruction scheduling by making modifications to key phases of a successful global register allocator. Experimental results indicate that this technique performs as well as and increasingly better than other techniques with an increasing number of registers without the complexity of the previous approaches. A second strategy, Register Allocation Sensitive Region scheduling (RASER), performs a global scheduling technique called region scheduling while keeping track of the number of live variables in each region. RASER creates regions with parallelism matching the amount of parallelism exploitable by the architecture and also reduces the number of live variables in a region in order to reduce the amount of spill code generated by the subsequent register allocation phase. In addition, the design and implementation of a Register Allocator which allocates over the Program dependent graph (RAP) is also presented. By basing the allocation on the program dependence graph, the register allocation phase may be more easily integrated and intertwined with other optimization analyses and transformations, including instruction scheduling." @default.
- W182448324 created "2016-06-24" @default.
- W182448324 creator A5004335411 @default.
- W182448324 date "1996-10-03" @default.
- W182448324 modified "2023-09-23" @default.
- W182448324 title "Cooperative register allocation and instruction scheduling" @default.
- W182448324 hasPublicationYear "1996" @default.
- W182448324 type Work @default.
- W182448324 sameAs 182448324 @default.
- W182448324 citedByCount "1" @default.
- W182448324 crossrefType "journal-article" @default.
- W182448324 hasAuthorship W182448324A5004335411 @default.
- W182448324 hasConcept C107568181 @default.
- W182448324 hasConcept C111919701 @default.
- W182448324 hasConcept C119948110 @default.
- W182448324 hasConcept C128916667 @default.
- W182448324 hasConcept C140763907 @default.
- W182448324 hasConcept C153247305 @default.
- W182448324 hasConcept C162262903 @default.
- W182448324 hasConcept C162324750 @default.
- W182448324 hasConcept C169590947 @default.
- W182448324 hasConcept C170595534 @default.
- W182448324 hasConcept C173608175 @default.
- W182448324 hasConcept C206729178 @default.
- W182448324 hasConcept C21547014 @default.
- W182448324 hasConcept C2781172179 @default.
- W182448324 hasConcept C2871975 @default.
- W182448324 hasConcept C41008148 @default.
- W182448324 hasConcept C68387754 @default.
- W182448324 hasConcept C73564150 @default.
- W182448324 hasConcept C98986596 @default.
- W182448324 hasConceptScore W182448324C107568181 @default.
- W182448324 hasConceptScore W182448324C111919701 @default.
- W182448324 hasConceptScore W182448324C119948110 @default.
- W182448324 hasConceptScore W182448324C128916667 @default.
- W182448324 hasConceptScore W182448324C140763907 @default.
- W182448324 hasConceptScore W182448324C153247305 @default.
- W182448324 hasConceptScore W182448324C162262903 @default.
- W182448324 hasConceptScore W182448324C162324750 @default.
- W182448324 hasConceptScore W182448324C169590947 @default.
- W182448324 hasConceptScore W182448324C170595534 @default.
- W182448324 hasConceptScore W182448324C173608175 @default.
- W182448324 hasConceptScore W182448324C206729178 @default.
- W182448324 hasConceptScore W182448324C21547014 @default.
- W182448324 hasConceptScore W182448324C2781172179 @default.
- W182448324 hasConceptScore W182448324C2871975 @default.
- W182448324 hasConceptScore W182448324C41008148 @default.
- W182448324 hasConceptScore W182448324C68387754 @default.
- W182448324 hasConceptScore W182448324C73564150 @default.
- W182448324 hasConceptScore W182448324C98986596 @default.
- W182448324 hasLocation W1824483241 @default.
- W182448324 hasOpenAccess W182448324 @default.
- W182448324 hasPrimaryLocation W1824483241 @default.
- W182448324 hasRelatedWork W1488677560 @default.
- W182448324 hasRelatedWork W1491378777 @default.
- W182448324 hasRelatedWork W1570671539 @default.
- W182448324 hasRelatedWork W1572089978 @default.
- W182448324 hasRelatedWork W1596795436 @default.
- W182448324 hasRelatedWork W18945967 @default.
- W182448324 hasRelatedWork W1998018454 @default.
- W182448324 hasRelatedWork W2065048619 @default.
- W182448324 hasRelatedWork W2110937681 @default.
- W182448324 hasRelatedWork W2121624795 @default.
- W182448324 hasRelatedWork W2162987996 @default.
- W182448324 hasRelatedWork W2169528027 @default.
- W182448324 hasRelatedWork W2171595223 @default.
- W182448324 hasRelatedWork W2269159438 @default.
- W182448324 hasRelatedWork W2352470693 @default.
- W182448324 hasRelatedWork W2353958330 @default.
- W182448324 hasRelatedWork W2380920873 @default.
- W182448324 hasRelatedWork W2889415077 @default.
- W182448324 hasRelatedWork W2059399861 @default.
- W182448324 hasRelatedWork W2182475594 @default.
- W182448324 isParatext "false" @default.
- W182448324 isRetracted "false" @default.
- W182448324 magId "182448324" @default.
- W182448324 workType "article" @default.