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- W1839791172 abstract "We describe a new test chip documentation methodology which simultaneously generates inputs for layout design and test chip documentation. On-line test chip documentation is generated based on specifications from the test structure requester/designer. This specification is used as input for both the layout designer and also for software which generates on-line test structure documentation. In addition, results from layout and circuit verification tools are compared with specifications to ensure that layout, specification, and documentation agree." @default.
- W1839791172 created "2016-06-24" @default.
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- W1839791172 date "2002-12-24" @default.
- W1839791172 modified "2023-09-26" @default.
- W1839791172 title "Automatic test chip documentation synthesis" @default.
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- W1839791172 doi "https://doi.org/10.1109/icmts.1996.535650" @default.
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