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- W1841730948 abstract "Summary form only given. This paper reports a CMOS inverter active power-delay product of less than 0.1 fJ/stage at 25/spl deg/C and at Vdd=0.1 V. We believe this is the lowest reported. This is accomplished by using a novel technique to match NFET and PFET subthreshold currents and, thus, enable operation of a standard 1.5 V 180 nm CMOS technology in subthreshold at very low Vdd. This technique uses voltage feedback to the MOSFET wells to match the NFET off current (Ioffn) and PFET off current (Ioffp), significantly enhancing the manufacturability of CMOS subthreshold logic." @default.
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- W1841730948 date "2002-11-13" @default.
- W1841730948 modified "2023-09-25" @default.
- W1841730948 title "Low-power CMOS at Vdd=4kT/q" @default.
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- W1841730948 doi "https://doi.org/10.1109/drc.2001.937856" @default.
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