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• W185031245 abstract "Mobile phones, music players, personal computers, set-top boxes and countless other digital electron-ics appliances are part of our daily life. These nomadic devices provide more and more functionality.As an example, recent mobile phones allow to communicate, to take pictures, to play video, to listento music, to watch TV, to browse the web, ... To achieve all this, the integrated circuit (IC) exe-cuting all these functions needs to become more and more complex. Moreover, since these devicesare mass-market products, the ICs have to be designed in a very short time.So far, circuit designers have handcrafted circuit architectures and translated them into a set ofconnected transistors by using low-level synthesis tools to obtain the IC layout. To cope with theincreasing circuit complexity and the shrinking time-to-market, however, new methods and tools arerequired. To achieve this, High-Level Synthesis (HLS) tools have been developed to automate thedesign of architectures. These tools accept as input an algorithmic specification that describes thefunctionality of the IC, which is written in a classical programming language (e.g. the C language).From this specification, High-Level Synthesis tools automatically generate an architecture com-posed of a processing unit and a control unit. The processing unit (also called data-path) includesoperators (A1), registers (R1, R2 and R3), multiplexers (M1), ports and wires. Operators processarithmetical and logical operations (equivalent to the machines in the manufacturing domain) andare connected, through wires (roads), to the registers (storage elements) which store data. Portsallow to get data from and provide data out of the circuit. Multiplexers are steering components.The control part allows writing into registers and drives the steering elements.Figure 1 depicts an architecture composed of four registers (R1, R2, R3 and R4), one adder(A1), one multiplexer (M1), ports (P1, P2 and P3), wires and a control unit. This architectureperforms the following operations. Input data is obtained from P1 and P2 to be stored in R1, R2and R3. The adder computes the sum of two selected registers and puts the result in R4. M1 isHamburg, Germany, July 13–16, 2009" @default.
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• W185031245 date "2009-05-11" @default.
• W185031245 modified "2023-10-18" @default.
• W185031245 title "VNS for High Level Synthesis" @default.
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