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- W1852838424 abstract "This paper presents a 1.2 V/2.5 V tolerant I/O buffer design with only thin gate-oxide devices. The novel floating N-well and gate-tracking circuits in mixed-voltage I/O buffer are proposed to overcome the problem of leakage current, which will occur in the conventional CMOS I/O buffer when using in the mixed-voltage I/O interfaces. The new proposed 1.2 V/2.5 V tolerant I/O buffer design has been successfully verified in a 0.13-/spl mu/m salicided CMOS process, which can be also applied in other CMOS processes to serve different mixed-voltage I/O interfaces." @default.
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- W1852838424 date "2004-10-04" @default.
- W1852838424 modified "2023-09-27" @default.
- W1852838424 title "Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-μm CMOS technology" @default.
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- W1852838424 doi "https://doi.org/10.1109/iscas.2004.1329337" @default.
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