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• W1859575013 abstract "We present CMOS transistors with n/sup +//p/sup +/ source/drain extensions doped by AsH/sub 3/ and BF/sub 3/ plasma immersion ion implantation (PIII) for the first time. We successfully demonstrate n/sup +//p/sup +/ shallow junctions with R/sub s/<1 k/spl Omega//sq for CMOS devices. No degradation in gate oxide integrity is observed for either AsH/sub 3/ or BF/sub 3/ PIII. Compared to conventional ion implantation, PIII provides much better short-channel effects and approximately 50% I/sub off/ reduction for both nMOS and pMOS devices. In particular, the flat threshold voltage roll-off and good performance in buried-channel pMOS devices is the best-reported PIII data to date." @default.
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• W1859575013 date "2002-11-13" @default.
• W1859575013 modified "2023-09-27" @default.
• W1859575013 title "Shallow n/sup +//p/sup +/ junction formation using plasma immersion ion implantation for CMOS technology" @default.
• W1859575013 cites W1998097934 @default.
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• W1859575013 doi "https://doi.org/10.1109/vlsit.2001.934927" @default.
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