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- W1861233896 abstract "An efficient VLSI architecture for 8/spl times/8 two-dimensional (2D) discrete cosine transform (DCT) is proposed in this paper. It is a folded architecture using direct method. It can compute 2D-DCT of a 12-b 8/spl times/8 block using one 1D-DCT unit without transpose memory. Taking advantage of the direct method, the total number of multiplications in the proposed architecture is only half of that required for row-column method. It, in turn, results in the doubled operating speed compared with those conventional implementations with row-column method. Under 0.6 /spl mu/m CMOS and double metal technology, the proposed architecture presents a chip with core size 3.9/spl times/0.9 mm/sup 2/, transistor count 114 K and clock rate 200 MHz." @default.
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- W1861233896 date "2002-11-13" @default.
- W1861233896 modified "2023-09-23" @default.
- W1861233896 title "An efficient VLSI architecture for 2D-DCT using direct method" @default.
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- W1861233896 doi "https://doi.org/10.1109/icasic.2001.982583" @default.
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