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• W1869721837 abstract "We introduce a new gate sizing rule for significantly improving the speed performance of static logic paths designed in submicron CMOS technology. This methodology is based on the definition of local gate sizing criterion. It is directly deduced from analytical models of the output transition time and of the short circuit power dissipation, which are validated on a 0.18 /spl mu/m CMOS process. This sizing methodology is shown to offer a low power implementation alternative that can be used as an initial solution, prior to any logic path optimization." @default.
• W1869721837 created "2016-06-24" @default.
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• W1869721837 date "2003-06-26" @default.
• W1869721837 modified "2023-09-27" @default.
• W1869721837 title "Gate speed improvement at minimal power dissipation" @default.
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• W1869721837 doi "https://doi.org/10.1109/apccas.2002.1115250" @default.
• W1869721837 hasPublicationYear "2003" @default.
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