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- W1870293527 abstract "A fast method to estimate the effects of line edge roughness is proposed. This method is based upon the use of multiple 2D device slices sandwiched together to form a MOS transistor of a given width. This method was verified to yield an accurate representation of rough edge MOS transistors through comparisons to full three dimensional simulations. A subsequent statistical study shows how the variation in line edge roughness affects the values and variances of several key device parameters." @default.
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- W1870293527 date "2002-11-07" @default.
- W1870293527 modified "2023-09-27" @default.
- W1870293527 title "Modeling line edge roughness effects in sub 100 nanometer gate length devices" @default.
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- W1870293527 doi "https://doi.org/10.1109/sispad.2000.871225" @default.
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