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- W1872717648 abstract "A novel charge-based comparator and folding circuit are presented. Correlated double sampling comparison is performed using a log-domain integrator, implemented by a subthreshold nMOS transistor with the source coupled to a capacitor. The circuit produces a current that is a logistic function of the change in voltage on the gate, with an input-referred offset voltage that is a logarithmic function of time. Folding operation for analog-to-digital conversion is obtained by differentially combining currents from a bank of these comparators. A prototype 128-channel parallel 4-bit gray-code analog-to-digital converter has been implemented in a 0.5 /spl mu/m CMOS process, delivering 128 MS/sec at 76 mW power dissipation." @default.
- W1872717648 created "2016-06-24" @default.
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- W1872717648 date "2003-06-25" @default.
- W1872717648 modified "2023-09-25" @default.
- W1872717648 title "Charge-based MOS correlated double sampling comparator and folding circuit" @default.
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- W1872717648 doi "https://doi.org/10.1109/iscas.2002.1010663" @default.
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