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- W1875426944 abstract "This work presents a compact methodology for power distribution network design in a nanometer scale VLSI chip using a noise-area tradeoff analysis which considers on-chip inductance effects. This methodology is used to quantitatively demonstrate the importance of considering on-chip power grid inductance, and how its impact scales with technology. While increasing power supply noise levels (which become worse with on-chip inductance) are expected to adversely impact the chip's power supply grid design, this work demonstrates that a power grid optimized with on-chip inductance considerations can lead to significant improvement in the wiring resource utilization." @default.
- W1875426944 created "2016-06-24" @default.
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- W1875426944 date "2005-03-31" @default.
- W1875426944 modified "2023-10-01" @default.
- W1875426944 title "Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits" @default.
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- W1875426944 doi "https://doi.org/10.1109/isqed.2005.64" @default.
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