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- W1883923933 abstract "In this paper two data cache architectures-a direct-mapped write-through data cache and a direct-mapped, write-through, write buffering data cache-are presented followed by a synthesized implementation of these data cache models. Strategies for testing, results of simulations with Verilog-XL/sup TM/ and methods of architectural improvement are also given." @default.
- W1883923933 created "2016-06-24" @default.
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- W1883923933 date "2003-01-20" @default.
- W1883923933 modified "2023-09-26" @default.
- W1883923933 title "An architectural survey and modeling of data cache memories in Verilog HDL" @default.
- W1883923933 doi "https://doi.org/10.1109/smicnd.1999.810448" @default.
- W1883923933 hasPublicationYear "2003" @default.
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