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• W1892314372 abstract "Merged logic and DRAM or processing-in-memory (PIM) devices are widely recognised as a mechanism to avoid the memory wall bottlenecks exhibited by modern computing platforms. As several design efforts are working on commodity DRAM replacement parts, we present a simulation architecture for a SIMD active memory enhanced workstation. Additionally, we show that actually making use of all the available bandwidth presented by a DRAM to on-chip logic will significantly degrade the performance of an interactive multitasking environment. In order to minimise this performance degradation, we present a modified data tiling technique to allow the SIMD array's register file to be used as a cache." @default.
• W1892314372 created "2016-06-24" @default.
• W1892314372 creator A5000762990 @default.
• W1892314372 creator A5084238814 @default.
• W1892314372 date "2004-03-23" @default.
• W1892314372 modified "2023-09-27" @default.
• W1892314372 title "System level simulation of a SIMD active memory enhanced PC (or, why we don't want 100% bandwidth utilisation)" @default.
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• W1892314372 doi "https://doi.org/10.1109/ipdps.2003.1213506" @default.
• W1892314372 hasPublicationYear "2004" @default.
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