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• W1892497341 abstract "Abstract We report on the design of a 4-bit flash ADC with dynamic offset correction dedicated to measurement systems based on a pixel architecture. The presented converter was manufactured in two CMOS technologies: widespread and economical 180 nm and modern 40 nm process. The designs are optimized for the lowest area occupancy resulting in chip areas of 160×55 µm 2 and 35×25 µm 2 . The experimental results indicate integral nonlinearity of +0.35/−0.21 LSB and +0.28/−0.25 LSB and power consumption of 52 µW and 17 µW at 5 MS/s for the prototypes in 180 nm and 40 nm technologies respectively." @default.
• W1892497341 created "2016-06-24" @default.
• W1892497341 creator A5060830638 @default.
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• W1892497341 date "2015-11-01" @default.
• W1892497341 modified "2023-10-03" @default.
• W1892497341 title "Low area 4-bit 5 MS/s flash-type digitizer for hybrid-pixel detectors – Design study in 180 nm and 40 nm CMOS" @default.
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• W1892497341 doi "https://doi.org/10.1016/j.nima.2015.08.028" @default.
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