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- W1895592702 abstract "This paper reports on a novel Super Junction LDMOST in SOS technology (SJ-LDMOST) targeting Power Integrated Circuits (PICs) and discusses a CMOS compatible process used in the implementation of the device. The proposed structure uses a simple and practical method to achieve charge compensation between the n and p SJ-pillars and a uniform electric field distribution in the forward blocking mode. 3D device simulations indicate that a significant reduction of the specific on-resistance for a given breakdown voltage can be achieved over conventional RESURF devices using a realistic aspect ratio for the SJ pillars." @default.
- W1895592702 created "2016-06-24" @default.
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- W1895592702 date "2003-06-25" @default.
- W1895592702 modified "2023-09-27" @default.
- W1895592702 title "Super junction LDMOST in silicon-on-sapphire technology (SJ-LDMOST)" @default.
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- W1895592702 doi "https://doi.org/10.1109/ispsd.2002.1016176" @default.
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