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- W1900681996 abstract "This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timing." @default.
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- W1900681996 date "2002-11-08" @default.
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- W1900681996 title "A programmable BIST architecture for clusters of multiple-port SRAMs" @default.
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- W1900681996 doi "https://doi.org/10.1109/test.2000.894249" @default.
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