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• W1900984856 abstract "A quad multi-speed (1.25/1.5625/2.5/3.125Gb/s) serializer/deserializer implemented in 0.25/spl mu/m CMOS technology is described. It uses a 4/spl times/ interleaved sample-and-hold receiver architecture. An analog adaptive receiver equalizer and a linear phase detector are used for clock and data recovery. At 3.125Gb/s, the serializer RMS jitter is 2.4ps. The serializer/deserializer runs error free for 2/sup 31/-1 PRBS data pattern over various length, up to 40-inches, of FR4 PCB trace." @default.
• W1900984856 created "2016-06-24" @default.
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• W1900984856 date "2004-10-26" @default.
• W1900984856 modified "2023-09-27" @default.
• W1900984856 title "A quad multi-speed serializer/deserializer with analog adaptive equalization" @default.
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• W1900984856 doi "https://doi.org/10.1109/vlsic.2004.1346609" @default.
• W1900984856 hasPublicationYear "2004" @default.
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