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- W1903405547 abstract "Three-dimensional integrated circuits (3D-ICs) composed of active circuit layers that are vertically stacked and interconnected are expected to lead to improved logic devices, memories, CPUs, and photosensors (Akasaka, 1986). These circuits require high-density vertical interconnections (3D vias) comparable in aspect ratio to present multilevel vias (Reber and Tielert, 1996). We have constructed and tested 3D ring oscillators and fully parallel 64/spl times/64 active pixel sensors using a 3D assembly technology which utilizes SOI wafers to achieve stacking of multiple circuit layers and unrestricted placement of dense 3D vias." @default.
- W1903405547 created "2016-06-24" @default.
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- W1903405547 date "2002-11-07" @default.
- W1903405547 modified "2023-10-17" @default.
- W1903405547 title "An SOI-based three-dimensional integrated circuit technology" @default.
- W1903405547 cites W2022397498 @default.
- W1903405547 doi "https://doi.org/10.1109/soi.2000.892749" @default.
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