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- W1903649743 abstract "We discuss a novel architecture for very high speed packet switching with priority-based conflict resolution. An input-queued switch with N/sup 2/ queues is used to prevent head-of-line blocking. Unlike previous designs which use multiple FIFO queues to provide several priority levels, we use hardware priority queues with 16-bit priority encoding. To reduce the hardware complexity, we introduce the concept of grouping fixed-size packets into ensembles that are stored by reference in the priority queues. This approach yields large buffer capacity while using relatively short queues." @default.
- W1903649743 created "2016-06-24" @default.
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- W1903649743 date "2003-01-20" @default.
- W1903649743 modified "2023-09-24" @default.
- W1903649743 title "A 40 Gb/s packet switching architecture with fine-grained priorities" @default.
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- W1903649743 doi "https://doi.org/10.1109/icccn.1999.805509" @default.
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