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- W1918967579 abstract "A multiple-valued current-mode MOS integrated circuit is proposed for high-speed arithmetic systems at low supply voltage. Since a multiple-valued source-coupled logic circuit with dual-rail complementary inputs results in a small signal-voltage swing while providing a constant driving current, the switching speed of the circuit is improved at low supply voltage. As an application to arithmetic systems, a high-speed parallel multiplier using a Booth-encoded algorithm and redundant code (which is realized by using multiple-valued MOS current-mode circuits) is designed. The performance of the proposed circuits is evaluated to be faster than that of a corresponding binary implementation under normal power dissipation. A prototype chip is fabricated to confirm the basic operation of the multiple-valued arithmetic circuit." @default.
- W1918967579 created "2016-06-24" @default.
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- W1918967579 date "2002-11-13" @default.
- W1918967579 modified "2023-09-27" @default.
- W1918967579 title "High-speed parallel multiplier with redundant-code algorithm using multiple-valued MOS current-mode circuits" @default.
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- W1918967579 doi "https://doi.org/10.1109/icasic.2001.982628" @default.
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