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• W1922637827 abstract "In the high-speed digital printed circuit board (PCB), there exists a layer capacitance (generally from 0.02 nF to 200 nF) between the closely spaced power and ground layers, which has some restriction on delta-I noise. According to the MPIE (mixed potential integral equation), a model is developed to analyze and characterize quantitatively the restriction on delta-I noise by the power/ground structure in PCB in high frequencies (from 100 MHz to 3 GHz). In comparison with the measured data from a testboard, the method produces relatively precise results. The restriction on delta-I noise is complicated by the high frequency and several strategies are provided to reduce the noise." @default.
• W1922637827 created "2016-06-24" @default.
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• W1922637827 date "2002-11-27" @default.
• W1922637827 modified "2023-09-26" @default.
• W1922637827 title "The restriction on delta-I noise along the power/ground layer in the highspeed digital printed circuit board" @default.
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• W1922637827 doi "https://doi.org/10.1109/isemc.1998.750146" @default.
• W1922637827 hasPublicationYear "2002" @default.
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