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• W1927096916 abstract "As leakage power and total power is a more and more dramatic issue is very deep submicron technologies, this paper explores new design methodologies for designing leakage tolerant digital architectures, based on architectural parameters like activity, logical depth, number of transitions for achieving a given task and total number of gates. Various architectures for a same logic function are compared at very low Vdd and VT that define the optimal total power consumption of each architecture." @default.
• W1927096916 created "2016-06-24" @default.
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• W1927096916 date "2004-12-23" @default.
• W1927096916 modified "2023-09-24" @default.
• W1927096916 title "Optimizing architecture activity and logic depth for static and dynamic power reduction" @default.
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• W1927096916 doi "https://doi.org/10.1109/newcas.2004.1359011" @default.
• W1927096916 hasPublicationYear "2004" @default.
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