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- W1927774803 abstract "The author reviews the early trends in 3-D WSI (wafer scale integration) and examines recent breakthroughs in technology to assess the viability of 3-D. It is concluded that this option is rich with possibility for the designer. However, not every architecture can benefit equally from this packaging approach. An attempt is made to quantify this impact by computing an average wire-shortening effect from 3-D partitioning, but even this average improvement is pessimistic if the given architecture is such that the most critical paths can all be placed on the vertical wiring runs in the stack, depending on the vertical spacing of the wafers. >" @default.
- W1927774803 created "2016-06-24" @default.
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- W1927774803 date "2002-12-09" @default.
- W1927774803 modified "2023-09-23" @default.
- W1927774803 title "An overview and analysis of 3D WSI" @default.
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- W1927774803 doi "https://doi.org/10.1109/icwsi.1991.151719" @default.
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