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- W1930629285 abstract "With the goal of reducing EMI generated by high frequency digital clocks, this paper describes a very flexible way of modulating the output of a standard PLL which provides more than 13 dB of power attenuation at the expense of a small and controlled increase of the clock jitter. The trade-offs are analyzed, and an implementation is presented with measurement results on a test chip." @default.
- W1930629285 created "2016-06-24" @default.
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- W1930629285 date "2003-01-20" @default.
- W1930629285 modified "2023-09-23" @default.
- W1930629285 title "A frequency modulated PLL for EMI reduction in embedded application" @default.
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- W1930629285 doi "https://doi.org/10.1109/asic.1999.806535" @default.
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