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- W1936769367 abstract "The paper describes a methodological framework that aims to apply formal design and verification techniques to the domain of logic control and supervision for manufacturing systems. The methodology is based on an object-oriented approach, supported by a syntactical and semantical adaptation of the semi-formal software specification languages UML and statecharts. The modeling languages have been subsequently formalized, according to a semantics that take into account the concepts described in the IEC 61131-3 standard for industrial controllers programming, in order to prove correctness properties expressed in the temporal logic CTL. The verification process is performed by means of the model-checking tool SMV." @default.
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- W1936769367 date "2004-01-24" @default.
- W1936769367 modified "2023-09-26" @default.
- W1936769367 title "Design and verification of industrial logic controllers with UML and statecharts" @default.
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- W1936769367 doi "https://doi.org/10.1109/cca.2003.1223152" @default.
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