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- W1938719005 abstract "Flexible programmability has become the key issue in polygon-based rasterization on 3D graphics hardware in endowing realism to the final image displayed. Yet, data parallelism must also be exploited in order to ensure performance at interactive rate. In this paper, a new hierarchical architecture based on both MIMD and SIMD, otherwise known as heterogeneous chip multiprocessing, is presented along with dynamically allocated nodes to provide load balancing in 3D graphics, physics simulation, and general-purpose programming." @default.
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- W1938719005 date "2008-10-01" @default.
- W1938719005 modified "2023-09-22" @default.
- W1938719005 title "Hierarchical Processing Architecture with Dynamically Allocated Nodes for 3D Graphics Shader" @default.
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