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• W1948778041 abstract "Although multiplying delay-locked loops allow clock frequency multiplication with very low phase noise and jitter, their application has been so far limited to integer-N multiplication, and the achieved reference-spur performance has been typically limited by time offsets. This paper presents the first published multiplying delay-locked loop achieving fine fractional-N frequency resolution, and introduces an automatic cancellation of the phase detector offset. Both capabilities are enabled by insertion of a digital-to-time converter in the reference path. The proposed synthesizer, implemented in a standard 65 nm CMOS process, occupies a core area of 0.09 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> , and generates a frequency ranging between 1.6 and 1.9 GHz with a 190 Hz resolution from a 50 MHz quartz-based reference oscillator. In fractional-N mode, the integrated RMS jitter, including random and deterministic components, is below 1.4 ps at 3 mW power consumption, leading to a jitter-power figure of merit of -232 dB. In integer-N mode, the circuit achieves RMS jitter of 0.47 ps at 2.4 mW power and figure of merit of -243 dB. Thanks to the adoption of the automatic offset cancellation, the reference-spur level is reduced from -32 to -55 dBc." @default.
• W1948778041 created "2016-06-24" @default.
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• W1948778041 date "2015-11-01" @default.
• W1948778041 modified "2023-09-24" @default.
• W1948778041 title "A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop" @default.
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• W1948778041 doi "https://doi.org/10.1109/jssc.2015.2473667" @default.
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