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- W1955801273 abstract "Iterative decoding techniques for modern capacity-approaching codes are currently dominating the choices for forward error correction in a plethora of applications. Turbo codes, proposed in 1993, triggered the breakthrough in channel coding techniques as these codes approach the Shannon capacity limit. This was followed by the rediscovery of low-density parity-check (LDPC) codes in the 1990s, originally proposed in 1963. These codes are presently ubiquitous in the context of mobile wireless communications among other application domains. In this dissertation, we focus on the aspects and challenges for conceiving energy efficient VLSI decoders aimed at mobile wireless applications. These nomadic devices are typically battery-operated and demand high energy efficiency along with high throughput performance on the smallest possible footprint. Moreover, these iterative decoders are typically one of the most power intensive components in the baseband processing chain of a wireless receiver. We address the aspects for designing energy efficient LDPC decoders. At the algorithmic level we investigate the tradeoff among error-correction performance, energy efficiency and implementation area for different choices of message computation kernels. At the architectural level we focus on the memory subsystem design of an LDPC decoder since this module is responsible for the majority of the implementation area and power consumption. Finally, at the system level, we propose dynamic power management strategies that rely upon iteration control and workload prediction that may be applied to both Turbo and LDPC decoders." @default.
- W1955801273 created "2016-06-24" @default.
- W1955801273 creator A5024213630 @default.
- W1955801273 date "2011-03-31" @default.
- W1955801273 modified "2023-09-27" @default.
- W1955801273 title "Aspects of Energy Efficient LDPC Decoders" @default.
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