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- W1956552029 abstract "A signed 8-bit pipelined multiplier has been implemented in a standard 1.0 /spl mu/m CMOS process. It was successfully tested up to 375 MHz. This performance was achieved using the true single-phase clocking technique, fine-grain pipelining, and merging the combinational logic into the pipeline registers." @default.
- W1956552029 created "2016-06-24" @default.
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- W1956552029 date "2002-11-19" @default.
- W1956552029 modified "2023-09-23" @default.
- W1956552029 title "A 375 MHz 1 μm CMOS 8-bit multiplier" @default.
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- W1956552029 doi "https://doi.org/10.1109/vlsic.1995.520665" @default.
- W1956552029 hasPublicationYear "2002" @default.
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