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- W1963657276 abstract "High performance delay-locked loop (DLL) is key to the high data rate chip-to-chip communication, suggesting the output jitter, due to power noise, bang-bang noise, temperature-voltage drift, etc, should be properly controlled. In this paper, high speed DRAM operation can be achieved by a dual loop DLL with various novel techniques; a new counting code with hysteretic bit-transitions can remove the large DAC glitches by preventing the binary bit-transitions in the locking states. A delay buffer, which is insensitive to the power supply fluctuations, is proposed. The voltage-temperature (VT) dependencies of the feedback path and the open clock path are balanced, minimizing the VT shift of the clock. As a result, the high-speed DRAM interface with the maximized setup/hold window can be accomplished." @default.
- W1963657276 created "2016-06-24" @default.
- W1963657276 creator A5089488753 @default.
- W1963657276 date "2005-04-01" @default.
- W1963657276 modified "2023-10-14" @default.
- W1963657276 title "Design Techniques of Delay-Locked Loop for Jitter Minimization in DRAM Applications" @default.
- W1963657276 doi "https://doi.org/10.1093/ietele/e88-c.4.753" @default.
- W1963657276 hasPublicationYear "2005" @default.
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