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• W1964255814 abstract "We present a physical modeling of tunneling currents through ultrathin high-/spl kappa/ gate stacks, which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-/spl kappa/ dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO/sub 2/ with and without NH/sub 3/-based interface layers, and ALD Al/sub 2/O/sub 3/ gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks in order to project their scalability for future CMOS applications." @default.
• W1964255814 created "2016-06-24" @default.
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• W1964255814 date "2003-02-01" @default.
• W1964255814 modified "2023-09-30" @default.
• W1964255814 title "Modeling of tunneling currents through HfO₂ and (HfO₂)_x(Al₂O₃)/sub 1-x/ gate stacks" @default.
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• W1964255814 doi "https://doi.org/10.1109/led.2002.807708" @default.
• W1964255814 hasPublicationYear "2003" @default.
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