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- W1964332234 abstract "Semiconductor technology evolution enables the design of resource-constrained battery-powered ultra-low-cost chips required for new market segments such as environment, urban life and body monitoring. Caches have been shown to be the main energy and area consumer in those chips. This paper proposes simple, hybrid-operation (high Vcc, ultra-low Vcc), single-Vcc domain Adaptive Performance-Predictable Low-Energy (APPLE) L1 cache designs based on replacing energy-hungry SRAM cells by more energy-efficient and smaller cells enhanced with extra cache lines set up in an adapted victim cache to still enable strong performance guarantees. APPLE caches are proven to largely outperform existing solutions in terms of energy and area efficiency." @default.
- W1964332234 created "2016-06-24" @default.
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- W1964332234 date "2013-05-29" @default.
- W1964332234 modified "2023-09-27" @default.
- W1964332234 title "APPLE" @default.
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- W1964332234 doi "https://doi.org/10.1145/2463209.2488837" @default.
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