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- W1964736058 abstract "A two-part SAT solver using a complete algorithm was developed and used to characterize the impact of eliminating memory bottleneck from SAT solving. The first is a VHDL model that describes the hardware needed to implement the solver whereas the second is a software simulator counterpart. Comparisons between the two versions of the solver revealed accelerations of 3 orders of magnitude of the hardware version over the software version. Comparisons were also made with other state-of-the-art hardware SAT solvers where accelerations were observed. Tests were also performed with the MiniSAT software solver which revealed more than acceptable run-times. Circuit frequency projections were also used to approximate problem execution times." @default.
- W1964736058 created "2016-06-24" @default.
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- W1964736058 date "2013-06-01" @default.
- W1964736058 modified "2023-10-01" @default.
- W1964736058 title "Exploring limits of parallelism in FPGA-based Boolean satisfiability" @default.
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- W1964736058 doi "https://doi.org/10.1109/meco.2013.6601319" @default.
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