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- W1965606938 abstract "A new ½ dual-injection locked frequency divider (dual-ILFD) with wide locking range and low-power consumption is proposed and developed together with a divide-by-2 current mode logic (CML) divider. ½ CML divider is connected at the output of ½ dual-ILFD for achieving constant output amplitude. The chip was fabricated using a 0.18-µm BiCMOS process. The ½ dual-ILFD enhances the locking range with low-power consumption through optimized load quality factor (Q <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>L</inf> ) and output current amplitude (i <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>OSC</inf> ) simultaneously, achieving a locking range of 692 MHz between 7.512 and 8.204 GHz, which is almost 10 times larger than a single-injection counterpart. The core of ½ dual-ILFD consumes 2.93 mA with 1.5 V supply." @default.
- W1965606938 created "2016-06-24" @default.
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- W1965606938 date "2013-02-01" @default.
- W1965606938 modified "2023-10-16" @default.
- W1965606938 title "Dual-injection-locked ½ divider with optimized VCO loaded Q and current" @default.
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- W1965606938 doi "https://doi.org/10.1109/ncc.2013.6487921" @default.
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