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- W1966173861 abstract "Demand for techniques to reduce verification time has been increasing in recent VLSI designs using sub-micron processes. The model order reduction (MOR) method by M.Celik et al. (2002) shortens verification time by reducing transfer functions order of the circuits. Employing the MOR method, we have developed a technique to analyze large scale power supply wirings of a whole DSP LSI chip. We have confirmed that our technique greatly improves circuit analysis capability maintaining sufficient accuracy." @default.
- W1966173861 created "2016-06-24" @default.
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- W1966173861 date "2007-10-01" @default.
- W1966173861 modified "2023-10-14" @default.
- W1966173861 title "VLSI power wiring noise analysis using MOR method" @default.
- W1966173861 cites W2541374461 @default.
- W1966173861 doi "https://doi.org/10.1109/icasic.2007.4415846" @default.
- W1966173861 hasPublicationYear "2007" @default.
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