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- W1966305830 abstract "This paper proposes a compact hardware (H/W) implementation for the MISTY1 block cipher, which is one of the ISO/IEC 18033-3 standard encryption algorithms. In designing the compact H/W, we focused on optimizing the implementation of FO/FI/FL functions, which are the main components of MISTY1. For this optimization, we propose three new methods; reducing temporary registers for the FO function, shortening the critical path for the FI function, and merging the FL/FL-1 functions. According to our logic synthesis on a 0.18-µm CMOS standard cell library based on our proposed methods, the gate size is 3.4Kgates, which is the smallest as far as we know." @default.
- W1966305830 created "2016-06-24" @default.
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- W1966305830 date "2010-01-01" @default.
- W1966305830 modified "2023-10-14" @default.
- W1966305830 title "Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher" @default.
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- W1966305830 doi "https://doi.org/10.1587/transfun.e93.a.3" @default.
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