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- W1966531164 abstract "Cu is studied as a candidate for low-resistance VLSI interconnection. Simulation studies show that for effective channel length less than 0.5 mu m, the RC time constant of interconnection is a major part of the total delay. By reducing the resistivity of the interconnect, the operating speed can be increased by more than 20% without any change in design rule. A selective electroless deposition process was used to solve the Cu patterning difficulty. Patterns of 2.2- mu m pitch have been achieved with this process. The copper contamination issue is also studied; dielectric films such as silicon oxynitride and silicon nitride are shown to be effective in stopping Cu diffusion. By coating a thin Ni film on Cu, Cu corrosion can be reduced from 0.2 mu /h to less than 0.05 mu m/h at 100 degrees C in 4% KCL solution. >" @default.
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- W1966531164 date "1989-09-01" @default.
- W1966531164 modified "2023-10-16" @default.
- W1966531164 title "Selective electroless copper for VLSI interconnection" @default.
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- W1966531164 doi "https://doi.org/10.1109/55.34730" @default.
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