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- W1966997186 abstract "Network on chip is an emerging technology which provides data reliability and high speed with less power consumption. With the technological advancements a large number of devices can be integrated into a single chip. So the communication between these devices becomes vital. The network on chip (NoC) router is used for such communication. This paper focuses on the design analysis of 10 port router. The delay (2.571ns) and power (80.98mW) is minimized by using crossbar switch. The proposed architecture of 10 port router is simulated and synthesized in Xilinx ISE 14.4 software." @default.
- W1966997186 created "2016-06-24" @default.
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- W1966997186 date "2015-01-01" @default.
- W1966997186 modified "2023-09-26" @default.
- W1966997186 title "Design and analysis of 10 port router for network on chip (NoC)" @default.
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- W1966997186 doi "https://doi.org/10.1109/pervasive.2015.7087013" @default.
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