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• W1967332589 abstract "The total latency of the arithmetic operations in the critical direct loop of the second-order all-pass IIR section is reduced using a special class of the elliptic transfer function and thus the maximum sample frequency is increased. This is achieved by implementing one of two multipliers per section as a binary shifter, that is, without any hardware in FPGA or VLSI implementations. The second multiplier is implemented with a small number of shifters and adders using the quantization of the coefficients and optimization. We derive new exact formulae for those coefficients and we avoid all unnecessary computations in the optimization. New exact formulae provide efficient, very fast, simple and highly accurate algorithm suitable for standard software packages such as MATLAB. An example of high-speed two-channel filter bank illustrates the application." @default.
• W1967332589 created "2016-06-24" @default.
• W1967332589 creator A5021866682 @default.
• W1967332589 creator A5063003484 @default.
• W1967332589 date "2003-01-01" @default.
• W1967332589 modified "2023-09-30" @default.
• W1967332589 title "Efficient Algorithm for the Design of High-Speed Elliptic IIR Filters" @default.
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• W1967332589 doi "https://doi.org/10.1078/1434-8411-54100168" @default.
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