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- W1968232011 abstract "Abstract The level 2 muon trigger for the upgraded D0 detector is based on finding either a track segment directly outside the calorimeter or a full track that includes hits on either side of the magnetized iron toroid. The architecture for Level 2 includes the use of a preprocessor which will be used to find the segments. Queueing simulation of the Level 2 architecture shows a strong dependence between deadtime and large events in the preprocessors when a serial computation is performed. By using a parallel preprocessor architecture where each individual processor focuses on a narrow path through the detector, the effect of large events or slow calculations on deadtime is eliminated. The CNAPS commercial parallel processor board is considered for the muon preprocessor." @default.
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- W1968232011 date "1997-04-01" @default.
- W1968232011 modified "2023-09-30" @default.
- W1968232011 title "A massively parallel processor for level 2 muon triggers at D0" @default.
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- W1968232011 doi "https://doi.org/10.1016/s0168-9002(97)00041-7" @default.
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