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- W1968442753 abstract "ASIC designing for analog mixed-signal ICs is bit complicated and time consuming. Model-based design allows us to complete all design steps for validating the design at the initial stages. In this work a 14 bit, 20 MSamples/s, 85 mW successive approximation analog-to-digital converter (ADC) suitable for use in RF applications is designed. Beginning with a high-level behavioral model of the ADC, the design is elaborated and synthesizable VeriLog code is generated. ADC is designed in Matlab's Simulink environment using system generator, simulated and synthesized using Xilinx's ISE 9.1i. Finally we prototyped model on Xilinx's Spartan-II FPGA board is presented, verified and results are presented." @default.
- W1968442753 created "2016-06-24" @default.
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- W1968442753 date "2011-01-01" @default.
- W1968442753 modified "2023-09-27" @default.
- W1968442753 title "FPGA prototype of 14 bit, 20msamples/S, 85 Mw successive approximation ADC suitable for RF applications" @default.
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- W1968442753 doi "https://doi.org/10.1145/1980022.1980202" @default.
- W1968442753 hasPublicationYear "2011" @default.
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